The present disclosure generally relates to semiconductor technology, and more particularly to semiconductor devices including gate dielectric layers of transistors and methods of fabricating the same.
Semiconductor devices including integrated circuits have been employed in various electronic systems. The integrated circuits of the semiconductor devices include a plurality of transistors, and a lot of effort has been attempted to increase the number of the transistors formed in a limited area of the semiconductor substrate for increasing an integrated density. The transistors may be determined based on dimension of active portions of the semiconductor substrate to be formed in the transistor. As the transistors are scaled down, the dimensions of active portions have been reduced. As the dimensions of the active portions are reduced, the transistors may seriously suffer from a narrow width effect and a short channel effect.
A gate dielectric layer in the transistors may be formed of an oxide layer which is grown by thermally oxidizing the active portions of the semiconductor substrate. During the thermal oxidation of the active portions, silicon atoms in the active portions may be bonded to oxygen atoms to cause a silicon loss phenomenon. As a result, widths of the active portions (for example, an active portion corresponding to a gate length), that is, channel widths of the transistors may be reduced. Reduction of the channel widths of the transistors may lead to increase of channel resistance (Rch) of the transistors. Even if the transistors are turned on, drain current of the transistors may be reduced to degrade characteristics of the transistors.
Each of dynamic random access memory (DRAM) devices includes a plurality memory cells, and each of the memory cells includes a single cell transistor and a single cell capacitor connected to the single cell transistor. As the channel widths of the cell transistors are reduced, the channel resistance of the cell transistor increases to reduce a sensing margin of a cell current that flows through bit line electrically connected to the cell transistor. The silicon loss phenomenon in the active portions may make it difficult to accurately control a thickness of the gate dielectric layer of the cell transistors. The silicon loss phenomenon may significantly degrade the characteristics of the memory cell transistors which are formed using a high process technology with a minimum feature size of 20 nanometers or less.